Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh et al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. When multiple tier structures are employed in a three-dimensional memory device, a joint region between vertically neighboring tier structures is prone to an etch damage during an anisotropic etch of horizontal portions of a memory film. Such an etch damage can induce an electrical short between vertical semiconductor channels and electrically conductive layers that function as word lines. A method of preventing such electrical shorts is thus desired.